(1) Field of the Invention
This invention relates to emitter-base processing, and more particularly, to layout for self-aligned emitter-base processing for any two or more terminal device.
(2) Description of Related Art
Heterojunction bipolar transistors (HBTs) are comprised of a heterostructure formed from two or more semiconductors having different bandgaps and a close lattice match. The structure of HBTs is similar to that of BJTs, with the exception that HBTs use a wider bandgap emitter. As disclosed in a publication by S. Noor Mohammand et al., titled “Fundamentals, performance and reliability of III-V compound semiconductor heterojunction bipolar transistors,” University of Illinois at Urbana-Champaign, Materials Research Laboratory & Coordinated Science Laboratory, the frequency performance in HBTs is governed by the vertical structure of the epitaxial layers, the layout design, and the processing methods. The layout design and the processing methods influence parasitics such as the capacitance across the extrinsic base-collector junction, contact resistances in series with the emitter, base, and collector, and inductance caused by interconnects and wires. In general, the largest component of the base-collector capacitance originates in the extrinsic base region used to contact the base layer of the transistor. Therefore, the purpose of any viable HBT processing is to reduce the space between the emitter and the base to lower emitter-base resistance to make the HBT operation faster, reduce the extrinsic base capacitance to allow for higher frequency operation of the HBT device, and finally reduce the contact (or ohmic) resistance. Most, if not all, of the parasitics may in general be assuaged by the use of self-alignment processes.
To obviate the above-mentioned parasitics in an HBT structure, it is critical to align the active emitter area, the emitter contact, and the base contact patterns with one another. In most cases, an aligned emitter contact metal can overlap with the extrinsic base area without causing a short in the emitter-base junction, which allows for a smaller spacing between the emitter and the base. This alignment may be achieved by purposeful design or by mere self-alignment of the base electrode under a “T” type emitter mesa structure, which may be etched using a variety of well-known technologies.
The U.S. Pat. Nos. 5,614,423 and 5,717,228, both to Matsuoka et al., disclose a conventional self-aligned HBT and a conventional method for self-aligned HBT fabrication. The entire disclosures of both U.S. Pat. Nos. 5,614,423 and 5,717,228 are incorporated herein by reference, and are hereinafter collectively referred to as Matsuoka et al. In summary, Matsuoka et al. describes a hexagonal shaped emitter layer that is patterned on the wafer such that all edges of the hexagon are along crystal planes that are suppose to undercut when wet etched.
In particular, as disclosed by Matsuoka et al., compound semiconductor HBTs are generally fabricated by epitaxially growing desired semiconductor layers including an emitter layer, a base layer, and a collector layer on a semiconductor substrate, with the crystal plane (100) taken as a main surface, etching some of the semiconductor layers thus obtained to form a mesa structure, and forming ohmic contacts on the emitter, base, and collector layers. In general, in crystallography, Miller indices enclosed in a parenthesis ( ) indicate a crystal plane, and those enclosed in brackets [ ] indicate direction. In addition, herein, in expressing Miller indices for planes or directions, negative indices are indicated by underlining.
As the prior art shown in FIG. 1A illustrates, the conventional HBT mesa structure may be comprised of a semi-insulate InP substrate 102, which has deposited thereon a n+-doped InGaAs collector contact layer 104, and a n−-doped or undoped InGaAs collector layer 106, and a p+-doped InGaAs base layer 108. The HBT mesa structure in its emitter region has an n−-doped InP emitter layer 110, a n+-doped InGaAs emitter contact layer 114, and an emitter electrode 116. The HBT also includes a base electrode 112 deposited on the base layer 108 and the emitter electrode 116.
The prior art FIG. 1B is the cross-sectional illustration of the same semiconductor device in the (011) plane that is shown in the prior art FIG. 1A, with the added layer of dielectric material 115. As illustrated, in most instances the fabricated semiconductor is generally covered with a deposit of dielectric material 115 to protect the entire device (including the emitter mesa structure 125) against outside elements, to allow for handling of the device, and to provide for a multiple level interconnect scheme, with each level having a specific circuit topography. An opening, a through, or a via 113, is then provided to allow access to the various layers, including the illustrated base metal layer 112 of the device through the dielectric material 115. The top (or plan) view 124 of the prior art emitter mesa structure 125 of FIG. 1B is illustrated in the prior art FIG. 1C. As illustrated, the base metal 112 is deposited such that the emitter mesa structure 125 is completely contained within, and surrounded by the base metal 112, and hence, only a single access mechanism 113 is used to access the base mesa.
Referring back to FIG. 1A, in the conventional HBT, the crystal orientation of the emitter region in the plane (100) is oriented in a direction parallel to the [011] or [011] direction. This means that when a semiconductor substrate 102 having a (100) plane in a main surface is used, its orientation flat is selected so as to be in the (011) plane where cleave facets tend to appear, i.e., in the direction parallel to the [011] direction. In general, wafers do not have a completely round circumference. Most wafers have two straight or flat sections along their circumference, which are referred to as major flat and a minor flat. In general, lithography equipment uses these non-rounded circumferential distortions as a reference or starting point to orient the wafers at a fixed topography, for eventual patterning. Hence, the orientation flat is used by lithographic equipment as a “compass” to the wafer topography to pattern wafers. Therefore, it is considered natural to set the direction of arranging the emitter so that it is parallel or vertical to the orientation flat or plane (011) of the main surface of the substrate 102. Nonetheless, the control of the crystal orientation of the emitter only in a direction parallel to the [011] or [011] directions raises a problem in relation to the anisotropy of the crystal upon wet etching.
Referring to the cross-sectional view in the (011) plane for the conventional HBT indicated by arrow 100, the layers of the HBT are aligned such that an under-cut 118 is formed underneath only two of the peripheral portions or sides of the emitter electrode 116 because of anisotropic wet etching. Wet etching is the process where the material to be etched is dissolved when immersed in a chemical solution. Usually a mask is used for selective etching of the material. A mask is an element that covers (or masks) a material to be etched for selective etching of that material. An anisotropic entity is one where its physical properties vary with direction. Hence, anisotropic etch is one in which the etch rate in the direction normal to the surface is much higher than in direction parallel to the surface. In other words, with anisotropic material, different etch rates take place at different directions within the same material. Therefore, with anisotropic etching, no undercutting takes place in certain directions, which means that the lateral distortion of pattern is minimized. Accordingly, due to the anisotropic nature of the illustrated crystal, an anisotropic wet etching takes place where in the [011] direction the emitter electrode 116 and base electrode 112 are not self-aligned (no undercutting), and cause a short (tapered or slanted edge 120) between the base electrode 112 and the emitter electrode 116 in the [011] direction. This is illustrated in the cross-section view in the (011) plane of the crystal, pointed to by the arrow 101. This is despite the under-cut 118 along the [011] direction of the emitter mesa structure. Hence, given the anisotropic nature of the crystal, it is not easy to make the base electrode 112 narrower, which would be advantageous in reducing the contact area between the base 108 and collector 106 to reduce parasitic capacitance, or reduce the spacing between the base 112 and the emitter 116 electrodes to reduce the distance for current flow, allowing faster operation of the HBT device.
As shown in the prior art FIG. 1A, the emitter mesa structure in the cross-sectional view of the (011) plane pointed by the arrow 100 is formed by wet etching and is in the form of a trapezoid with its lower edge (layer 110) being shorter than its upper edge (layer 116), which forms the under-cut 118 to form the “T” like mesa structure. This is the cross-sectional view in the (011) plane taken along the direction parallel to the [011] direction. On the contrary, as illustrated in the cross-section view in the (011) plane indicated by the arrow 101, along a direction parallel to the [011] direction, the emitter mesa is in the form of a trapezoid with its upper edge (layer 116) being shorter than its lower edge (layer 110), with the trapezoid non-parallel edges forming an outwardly slanted or tapered structure 120.
In anisotropic wet etching (due to the anisotropic nature of the crystal), the wet etching proceeds along a vertical direction so that the base layer 108 is exposed, but the side etching along the [011] direction does not proceed substantially, which causes the outwardly slanted structure 120 to form. Under these conditions, the method for fabricating a self-alignment structure by the deposition of a base metal for the formation of the base electrode 112 on the surface of the semiconductor substrate in the region that includes the emitter mesa gives a structure in which the base electrode 112 tends to contact the emitter layer 110 in a cross-section of the outwardly slant form 120. If the base electrode 112 contacts the emitter layer 110 (through the coating of the base metal 112 on the outwardly slant form 120), leakage current that flows between the emitter 110 and base 108 increases, reducing the current gain. In some cases, an emitter-base short occurs between the base electrode 112 and the emitter electrode 116, so that the HBT device cannot operate as a transistor at all.
The prior art FIG. 1D illustrates the solution proposed by Matsuoka et al. to try to overcome the problems associated with the anisotropic wet etching along the [011] direction of the crystal. As illustrated, the Matsuoka et al. disclosed a hexagonal shaped emitter layer 116 that is patterned on the wafer such that all edges of the hexagon are along crystal planes that are suppose to undercut when wet etched. In other words, the process should allow for isotropic wet etching due to the isotropic nature of the crystal along the illustrated directions. The region where the emitter electrode is to be provided is defined such that the crystal orientation in the plane (100) in which the emitter is defined is parallel to any of the [001], [010] and [011] directions. In other words, the crystal orientation defining the emitter in the plane (100) is restricted to a direction other than the [011] direction so that no over-cut mesa such as the slant 120 illustrated in the prior art FIG. 1A should appear. The top (or plan) view 134 of the prior art emitter mesa structure 135 is illustrated in the prior art FIG. 1E. As illustrated, the base metal 112 is deposited such that the emitter mesa structure 135 is completely contained within, and surrounded by the base metal 112, and hence, only a single access mechanism 113 is used to access the base mesa.
Referring back to the prior art FIG. 1D, the four-edged emitter 116 is transformed into a six edge emitter, with intersecting points 130 and 132 appearing between edges along the [010] and [001] directions on the periphery of an emitter electrode region. The ends of the emitter-base junction 150 and 152 (illustrated in the cross-sectional view in the (011) plane indicated by the arrow 101), underneath the line connecting the intersecting points 130 and 132 seem to have replaced the slanted or tapered edges 120 illustrated in FIG. 1A. As illustrated, the base electrode material 112 is also deposited on the emitter electrode 116 as shown. However, in the cross-section along the (011) plane indicated by arrow 100, an under-cut mesa seems to appear, so that the electric isolation between the emitter and base seems to be perfect.
When viewed in the (011) plane (indicated by arrow 100), the cross section or profile is in the form of an outward slant (not shown), and on the face of it, there could be the danger of an emitter-base short or an increase in leakage current between the emitter and base. However, the emitter electrode 116 does not seem to have any edge that is parallel to the [011] direction, but instead its edges seem to be defined in directions parallel to the [010] and [001] directions, as indicated by arrows A and B, respectively. Since etching along the [001] or [010] direction, like the etching along the [011] direction, proceeds symmetrically, the points 150 and 152 where the emitter-base junction seem to be exposed, and seem to move or be retreated toward the inside of the emitter electrode 116. This is because etching from both sides seems to proceed uniform in the intersecting points 130 and 132 between the edges parallel to the [010] and [001] directions on the periphery of the emitter electrode region. Therefore, perfect electrical isolation between the emitter and base seem to be achieved, even in the cross-section as viewed in the (011) or (011) planes.
Matsuoka et al. further disclosed another example, where the layer structure of the crystal and fabrication process for fabricating the HBT is substantially the same, but the crystal orientation of the emitter electrode is defined in the (100) plane by two edges parallel to the [010] direction, and two edges parallel to the [001] direction. In this case, the emitter mesa is surrounded by the (001), (010), (001), and (010) planes where etching proceeds vertically and at the same rate so that an under-cut seem to be formed along the entire periphery of the emitter mesa.
The disadvantage of the teachings of Matsuoka et al. is that it is nearly impossible or difficult to pattern a perfectly sharp angle (or corner) to create perfect intersecting points 130 and 132, to avoid the emergence of any unwanted edge along the [011] direction. As illustrated in FIG. 1F, which shows the magnified or enlarged intersecting point 130, some rounding of the resist pattern parallel along the [011] direction will undoubtedly occur, creating an edge 131 along the [011] direction. However, as was described above, due to the anisotropic nature of the crystal, the edge 131 will not undercut in the [011] direction, and will remain exposed. This edge 131 will create the same problems that were described and illustrated in relation to FIG. 1A, with respect to the slanted or tapered edges 120. One could surmise that the variation in the self-aligned device of Matsuoka et al. is caused by the variation in the sharpness of the corners 130 and 132.
Accordingly, in light of the current state of the art and the drawbacks to current semiconductor mesa structures and methods of fabrications thereof mentioned above, a need exists for a semiconductor mesa structure and a method of fabrication thereof that would allow for self-aligned emitter-base transistors when the only etches available for the emitter material do not undercut the emitter metal along one of the crystal planes to establish a reliable electric isolation between an emitter and a base.